The invention relates to technology for designing and verifying an integrated circuit (“IC”) design.
An IC has a large number of electronic components, such as transistors, logic gales, diodes, wires, etc., that are fabricated by forming layers of different materials and of different geometric shapes on various regions of a silicon wafer. The design of an integrated circuit transforms a circuit description into a geometric description called a layout. The process of converting specifications of an integrated circuit into a layout is called the physical design. After the layout is complete, it is then checked to ensure that it meets the design requirements. The result is a set of design files, which are then converted into pattern generator files. The pattern generator files are used to produce patterns called masks by an optical or electron beam pattern generator. Subsequently, during fabrication of the IC, these masks are used to pattern chips on the silicon wafer using a sequence of photolithographic steps. Electronic components of the IC are therefore formed on the wafer in accordance with the patterns.
Many phases of physical design may be performed with computer aided design (CAD) tools or electronic design automation (EDA) systems. To design an integrated circuit, a designer first creates high level behavior descriptions of the IC device using a high-level hardware design language. An EDA system typically receives the high level behavior descriptions of the IC device and translates this high-level design language into netlists of various levels of abstraction using a computer synthesis process. A netlist describes interconnections of nodes and components on the chip and includes information, for example, of circuit primitives such as transistors and diodes, their sizes and interconnections.
An integrated circuit designer may uses a set of layout EDA application programs to create a physical integrated circuit design layout from a logical circuit design. The layout EDA application uses geometric shapes of different materials to create the various electrical components on an integrated circuit and to represent electronic and circuit IC components as geometric objects with varying shapes and sizes.
After an integrated circuit designer has created an initial integrated circuit layout, the integrated circuit designer then tests and optimizes the integrated circuit layout using a set of EDA testing and analysis tools. Common testing and optimization steps include extraction, verification, and compaction. The steps of extraction and verification are performed to ensure that the integrated circuit layout will perform as desired. The test of extraction is the process of analyzing the geometric layout and material composition of an integrated circuit layout in order to “extract” the electrical characteristics of the designed integrated circuit layout. The step of verification uses the extracted electrical characteristics to analyze the circuit design using circuit analysis tools.
Common electrical characteristics that are extracted from an integrated circuit layout include capacitance and resistance of the various “nets” (electrical interconnects) in the integrated circuit. These electrical characteristics are sometimes referred to as “parasitic” since these are electrical characteristics are not intended by the designer but result from the underlying physics of the integrated circuit design. For example, when an integrated circuit designer wishes to connect two different locations of an integrated circuit with an electrical conductor, the electrical circuit designer would ideally like perfect conductor with zero resistance and zero capacitance. However, the geometry of a real conductor, its material composition, and its interaction with other nearby circuit elements will create some parasitic resistance and parasitic capacitance. The parasitic resistance and parasitic capacitance affect the operation of the designed integrated circuit. Thus, the effect of the parasitic resistance and parasitic capacitance on the electrical interconnect must be considered.
To test an integrated circuit layout, the integrated circuit designer ‘extracts’ parasitic resistance and parasitic capacitance from the integrated circuit layout using an extraction application program. Then, the integrated circuit designer analyzes and possibly simulates the integrated circuit using the extracted parasitic resistance and parasitic capacitance information. If the parasitic resistance or parasitic capacitance causes undesired operation of the integrated circuit, then the layout of the integrated circuit must be changed to correct the undesired operation. Furthermore, minimizing the amount of parasitic resistance and parasitic capacitance can optimize the performance of the integrated circuit by reducing power consumption or increasing the operating speed of the integrated circuit.
Copper interconnect has become the mainstream at 130 nm or beyond because of its advantages such as its lower resistivity and power consumption and better resistance to electromigration compared to aluminum. On the other hand, copper interconnect has also brought challenges to manufacturing of integrated circuits because of the effects resulting form the interaction between copper interconnects and the neighboring dielectric materials, especially in the chemical-mechanical polishing (CMP) process. A typical effect of these effects comprises thickness variation due to copper dishing and/or dielectric erosion. The thickness variation presents an even more profound problem in multi-layer designs. In order to compensate for the thickness variations, dummy metal fills have been developed and introduced into electronic circuit designs to ensure that the electronic circuit designs meet the metal density requirement usually imposed by foundries.
With the continual effort to shrink the feature size of electronic circuit designs, various model-based, as opposed to rule-based, approaches have been proposed to minimize or better control the thickness variations. These approaches typically optimizes the design or minimizes the thickness variations by taking into account the topographic profiles of the copper layer including the copper layer by electrochemical plating and copper seed layer by a deposition process, and a barrier layer such as a tantalum or a tantalum-nitride layer. Some model-based approaches may even take one or more of the underlying layers into account to evaluate the cumulative effects of a multi-layer electronic circuit design. These modes-based approaches often give more accurate prediction or estimate of the topography or other attributes of the electronic circuit design. Nonetheless, these model-based approaches almost always involve intensive computation in simulation and thus are usually implemented for the later stages of the electronic circuit design such as the sign-off/design closure stage.
Lithography simulation has recently gathered more attention in the past decades or two because of the increasing cost in manufacturing photomasks and development time to redesign and remanufacture a revised set of photomasks in case of a error in the design of the masks. With the advance of deep submicron technologies, resolution enhancement techniques (RET) have become one of the most important techniques to guarantee design for manufacturability (DFM).
Nonetheless, RET may pose further challenges to the integrated circuit (IC) design due to the continual pursuit for smaller geometry size and the use of shorter wavelength on the lithographic tools such as the 193 nm λ ultra-high numerical aperture (NA) lithography or even the Extreme Ultra Violet lithography, especially in the deep submicron and increasing clock frequency designs. For example, in order to meet the increasing demand for higher resolution and finer geometries, the semiconductor industry has been pushing in order to obtain larger numerical aperture (NA) to achieve smaller minimum feature size. However, larger numerical aperture also decreases the depth of focus, and such decreased depth of focus causes the lithographic tools' ability to print accurate circuits to be more sensitive to the topographical variation of the films on the wafer. This continual push towards smaller feature sizes and higher clock frequencies has made lithographic simulation even more important.
Moreover, for semiconductor manufacturing process nodes of 65 nm and beyond, accurate modeling of variations caused by various semiconductor manufacturing processes (e.g., a chemical-mechanical polishing (CMP), an etch process, or a lithography process) or other aspects of the electronic circuit has become more critical for modern electronic circuit designs in order to, for example, achieve higher yield or improve performance of the electronic circuit designs. As a result, physics-based modeling has been introduced to predict, for example, the thickness and/or topographic variations of each layer caused by one or more manufacturing processes Such as the CMP process. Some of these physics-based models have demonstrated that by using a predicted location and design specific thickness profile, the extraction tool can usually extract more accurate RC values. These physics-based models, although prove to be quite useful at later stages, such as the sigh-off stage, of the electronic circuit design, usually require long simulation time and thus are of limited usefulness for the earlier stages of die electronic circuit designs such as floor planning, place and route, and post route optimization.
Nonetheless, with the continual push for smaller features and high clock frequencies, there is a need for accounting for the variations or other aspects of the electronic circuit designs at the early stages of the electronic circuit design process. Unlike the physics-based models, conventional rule-based approaches produce the results within a shorter period of time, yet the accuracy of such results may not meet the requirements of modern electronic circuit designs. For example, during design stages such as floor planning, place and route, or post route optimization, minimizing design closure time is essential as multiple iterations are usually performed to find a desired solution based upon one or more design metrics such as congestion, timing, power, and chip size, etc. At these early design stages, knowledge of, for example, thickness variation of a particular layer may help circuit designers assess the performance of the circuit more realistically and accurately and thereby select a better floor plans and/or routes.
On the other hand, circuit designers are often presented with additional challenges during the early design stages such as floor planning, place and route, and post route optimization. For example, there may still exist some unknowns of the circuit which are not yet solved for or finalized during these early stages, and the accuracy requirements for the design metrics and/or the manufacturing process modeling may not be the same as those of the later stages such as the sign offstage.
Therefore, there exists a need for a method, system, and computer program product for implementing a compact manufacturing model which accounts for the significant physical effects to afford a circuit designer a sliding scale to find a perfect balance between speed in finding a set of results for the electronic circuit design and accuracy of the design for all stages of the electronic circuit designs including the early stages of the electronic circuit design such as floor planning, place and route, and post route optimization.